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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">HCPTR, Hyp Architectural Feature Trap Register</h1><p>The HCPTR characteristics are:</p><h2>Purpose</h2>
        <p>Controls:</p>

      
        <ul>
<li>Trapping to Hyp mode of Non-secure access, at EL1 or EL0, to trace, and to Advanced SIMD and floating-point functionality.
</li><li>Hyp mode access to trace, and to Advanced SIMD and floating-point functionality.
</li></ul>

      
        <div class="note"><span class="note-header">Note</span><p>Accesses to this functionality:</p><ul><li>From Non-secure modes other than Hyp mode are also affected by settings in the <a href="AArch32-cpacr.html">CPACR</a> and <a href="AArch32-nsacr.html">NSACR</a>.</li><li>From Hyp mode are also affected by settings in the <a href="AArch32-nsacr.html">NSACR</a>.</li></ul><p>Exceptions generated by the <a href="AArch32-cpacr.html">CPACR</a> and <a href="AArch32-nsacr.html">NSACR</a> controls are higher priority than those generated by the HCPTR controls.</p></div>
      <h2>Configuration</h2><p>AArch32 System register HCPTR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-cptr_el2.html">CPTR_EL2[31:0]</a>.</p><p>This register is present only when EL2 is capable of using AArch32. Otherwise, direct accesses to HCPTR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p>If EL2 is not implemented, this register is <span class="arm-defined-word">RES0</span> from EL3.</p>
      <h2>Attributes</h2>
        <p>HCPTR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">TCPAC</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_30-1">TAM</a></td><td class="lr" colspan="9"><a href="#fieldset_0-29_21">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20">TTA</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">TASE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-13_12">RES1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-11_11-1">TCP11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-10_10-1">TCP10</a></td><td class="lr" colspan="10"><a href="#fieldset_0-9_0">RES1</a></td></tr></tbody></table><h4 id="fieldset_0-31_31">TCPAC, bit [31]</h4><div class="field">
      <p>Traps Non-secure EL1 accesses to the <a href="AArch32-cpacr.html">CPACR</a> to Hyp mode.</p>
    <table class="valuetable"><tr><th>TCPAC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Non-secure EL1 accesses to the <a href="AArch32-cpacr.html">CPACR</a> are trapped to Hyp mode.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p>The <a href="AArch32-cpacr.html">CPACR</a> is not accessible at EL0.</p>
      </div>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When the PE resets into EL2 or EL3,
            this field resets to
            <span class="binarynumber">0</span>.
</li>
          
            <li>Otherwise,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul></div><h4 id="fieldset_0-30_30-1">TAM, bit [30]<span class="condition"><br/>When FEAT_AMUv1 is implemented:
                        </span></h4><div class="field">
      <p>Trap Activity Monitor access. Traps Non-secure EL1 and EL0 accesses to all Activity Monitor registers to EL2.</p>
    <table class="valuetable"><tr><th>TAM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Accesses from Non-secure EL1 and EL0 to Activity Monitor registers are not trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Accesses from Non-secure EL1 and EL0 to Activity Monitor registers are trapped to Hyp mode.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When the PE resets into EL2 or EL3,
            this field resets to
            <span class="binarynumber">0</span>.
</li>
          
            <li>Otherwise,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul></div><h4 id="fieldset_0-30_30-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-29_21">Bits [29:21]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-20_20">TTA, bit [20]</h4><div class="field">
      <p>Traps Non-secure System register accesses to all implemented trace registers to Hyp mode.</p>
    <table class="valuetable"><tr><th>TTA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Any Non-secure System register access to an implemented trace register is trapped to Hyp mode, unless the access is trapped to EL1 by a <a href="AArch32-cpacr.html">CPACR</a> or <a href="AArch32-nsacr.html">NSACR</a> control, or the access is from Non-secure EL0 and the definition of the register in the appropriate trace architecture specification indicates that the register is not accessible from EL0. A trapped instruction generates:</p>
<ul>
<li>A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1.
</li><li>An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.
</li></ul></td></tr></table><p>If the implementation does not include a trace unit, or does not include a System register interface to the trace unit registers, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether this bit:</p>
<ul>
<li>Is <span class="arm-defined-word">RES0</span>.
</li><li>Is <span class="arm-defined-word">RES1</span>.
</li><li>Can be written from Hyp mode, and from Secure Monitor mode when <a href="AArch32-scr.html">SCR</a>.NS is 1.
</li></ul>
<p>If EL3 is implemented and is using AArch32, and the value of <a href="AArch32-nsacr.html">NSACR</a>.NSTRCDIS is 1, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.</p>
<div class="note"><span class="note-header">Note</span><ul><li>The ETMv4 architecture and ETE do not permit EL0 to access the trace registers. If the trace unit implements FEAT_ETMv4 or FEAT_ETE, EL0 accesses to the trace registers are <span class="arm-defined-word">UNDEFINED</span>, and a resulting Undefined Instruction exception is higher priority than a HCPTR.TTA Hyp Trap exception.</li><li>The Arm architecture does not provide traps on trace register accesses through the optional memory-mapped debug interface.</li></ul></div><p>System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When the PE resets into EL2 or EL3,
            this field resets to
            <span class="binarynumber">0</span>.
</li>
          
            <li>Otherwise,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul></div><h4 id="fieldset_0-19_16">Bits [19:16]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_15">TASE, bit [15]</h4><div class="field">
      <p>Traps Non-secure execution of Advanced SIMD instructions to Hyp mode when the value of HCPTR.TCP10 is 0.</p>
    <table class="valuetable"><tr><th>TASE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>When the value of HCPTR.TCP10 is 0, any attempt to execute an Advanced SIMD instruction in Non-secure state is trapped to Hyp mode, unless it is trapped to EL1 by a <a href="AArch32-cpacr.html">CPACR</a> or <a href="AArch32-nsacr.html">NSACR</a> control. A trapped instruction generates:</p>
<ul>
<li>A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1.
</li><li>An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.
</li></ul></td></tr></table><p>When the value of HCPTR.TCP10 is 1, the value of this field is ignored.</p>
<p>If the implementation does not include Advanced SIMD and floating-point functionality, this field is <span class="arm-defined-word">RES1</span>. Otherwise, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether this field is implemented as a RW field. If it is not implemented as a RW field, then it is RAZ/WI.</p>
<p>If EL3 is implemented and is using AArch32, and the value of <a href="AArch32-nsacr.html">NSACR</a>.NSASEDIS is 1, in Non-secure state this field behaves as RAO/WI, regardless of its actual value. This applies even if the field is implemented as RAZ/WI.</p>
<p>For the list of instructions affected by this field, see <span class="xref">'Controls of Advanced SIMD operation that do not apply to floating-point operation'</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When the PE resets into EL2 or EL3,
            this field resets to
            <span class="binarynumber">0</span>.
</li>
          
            <li>Otherwise,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul></div><h4 id="fieldset_0-14_14">Bit [14]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-13_12">Bits [13:12]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-11_11-1">TCP11, bit [11]<span class="condition"><br/>When FEAT_FP is implemented and FEAT_AdvSIMD is implemented:
                        </span></h4><div class="field"><p>The value of this field is ignored. If this field is programmed with a different value to the TCP10 bit then this field is <span class="arm-defined-word">UNKNOWN</span> on a direct read of the HCPTR.</p>
<p>If the implementation does not include Advanced SIMD and floating-point functionality, this field is <span class="arm-defined-word">RES1</span>.</p>
<p>If EL3 is implemented and is using AArch32, and the value of <a href="AArch32-nsacr.html">NSACR</a>.cp10 is 0, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When the PE resets into EL2 or EL3,
            this field resets to
            <span class="binarynumber">0</span>.
</li>
          
            <li>Otherwise,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul><p>Accessing this field has the following behavior:</p><ul><li>
            Access is <span class="access_level">RAO/WI</span> if
                
                    all of the following are true:
                <ul><li>EL3 is implemented</li><li>EL3 is using AArch32</li><li>!IsCurrentSecurityState(SS_Secure)</li><li>NSACR.cp10 == 0</li></ul></li></ul></div><h4 id="fieldset_0-11_11-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-10_10-1">TCP10, bit [10]<span class="condition"><br/>When FEAT_FP is implemented and FEAT_AdvSIMD is implemented:
                        </span></h4><div class="field">
      <p>Trap Non-secure accesses to Advanced SIMD and floating-point functionality to Hyp mode:</p>
    <table class="valuetable"><tr><th>TCP10</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Any attempted access to Advanced SIMD and floating-point functionality from Non-secure state is trapped to Hyp mode, unless it is trapped to EL1 by a <a href="AArch32-cpacr.html">CPACR</a> or <a href="AArch32-nsacr.html">NSACR</a> control. A trapped instruction generates:</p>
<ul>
<li>A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1.
</li><li>An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.
</li></ul></td></tr></table><p>The Advanced SIMD and floating-point features controlled by these fields are:</p>
<ul>
<li>Execution of any floating-point or Advanced SIMD instruction.
</li><li>Any access to the Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15.
</li><li>Any access to the <a href="AArch32-fpscr.html">FPSCR</a>, <a href="AArch32-fpsid.html">FPSID</a>, <a href="AArch32-mvfr0.html">MVFR0</a>, <a href="AArch32-mvfr1.html">MVFR1</a>, <a href="AArch32-mvfr2.html">MVFR2</a>, or <a href="AArch32-fpexc.html">FPEXC</a> System registers.
</li></ul>
<p>If the implementation does not include Advanced SIMD and floating-point functionality, this field is <span class="arm-defined-word">RES1</span>.</p>
<p>If EL3 is implemented and is using AArch32, and the value of <a href="AArch32-nsacr.html">NSACR</a>.cp10 is 0, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset:<ul>
            <li>When the PE resets into EL2 or EL3,
            this field resets to
            <span class="binarynumber">0</span>.
</li>
          
            <li>Otherwise,
            this field resets to
            an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li>
          </ul></li></ul><p>Accessing this field has the following behavior:</p><ul><li>
            Access is <span class="access_level">RAO/WI</span> if
                
                    all of the following are true:
                <ul><li>EL3 is implemented</li><li>EL3 is using AArch32</li><li>!IsCurrentSecurityState(SS_Secure)</li><li>NSACR.cp10 == 0</li></ul></li></ul></div><h4 id="fieldset_0-10_10-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><h4 id="fieldset_0-9_0">Bits [9:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing HCPTR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b100</td><td>0b0001</td><td>0b0001</td><td>0b010</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T1 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T1 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x03);
    else
        R[t] = HCPTR;
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        UNDEFINED;
    else
        R[t] = HCPTR;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b100</td><td>0b0001</td><td>0b0001</td><td>0b010</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T1 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T1 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; !ELUsingAArch32(EL3) &amp;&amp; CPTR_EL3.TCPAC == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.AArch32SystemAccessTrap(EL3, 0x03);
    else
        HCPTR = R[t];
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        UNDEFINED;
    else
        HCPTR = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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